Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are synthesis, placement, and routing of the system on the target device.
After a system has been synthesized, placed, and routed on a target device, it is important that the system achieves timing closure where all timing constraints in the system are met in order to ensure proper functionality. A timing analysis is performed by the EDA tool to determine whether timing closure is achieved.
Rise/fall skew (rise/fall delay) is a material effect present in modern target devices. Rise/fall skew occurs when there is a difference in the rise time and fall time required for pulling up and pulling down a signal at a node. Some target devices, such as FPGAs, rely more heavily on NMOS pass gates to implement programmable switches. Due to the asymmetric rise/fall characteristics of NMOS pass gates, rise/fall skew is found to be more prevalent in data paths in FPGAs.
In the past, rise/fall skew has generally been small relative to path delay. As a result, traditional timing analysis performed by EDA tools did not adequately analyze the impact of rise/fall skew at the intermediate nodes along a data path. However, with the current trend of systems experiencing greater rise/fall skew, such traditional timing analysis may erroneously report that a system achieves timing closure when, in fact, it will fail to function in silicon.